The invention generally relates to an oscillating divider topology.
A conventional integrated circuit may have many different clock domains that span across the circuit. Because an ever-increasing number of devices are fabricated onto the integrated circuit, the number of clock domains on the integrated circuit typically increase from one generation to the next.
Challenges may arise in accommodating a large number of clock domains on a single integrated circuit in that it may take a significant number of clock cycles for a signal to propagate from one side of the integrated circuit to another. Asynchronous circuits are not synchronized to a clock signal, and therefore, asynchronous circuits provide a solution to the above-described problem with synchronized circuits. Instead of being synchronized to a clock signal, an asynchronous circuit is self-timed, which means the circuit uses a handshake protocol (and thus, not a clock signal) for purposes of communicating signals. One such protocol, called a quasi delay insensitive (QDI) protocol, adheres to the strictest asynchronous standard.
Pursuant to a QDI cycle, a transmitter may communicate data to a receiver in the following manner. Before driving its output terminals with data to be communicated to the receiver, the transmitter waits for the receiver to assert an acknowledge signal indicating that the receiver is able to receive new data from the transmitter. Thus, upon assertion of the acknowledge signal, the transmitter drives its output signals to indicate a particular data value. To indicate receipt of the data, the receiver de-asserts the acknowledge signal. After the de-assertion of the acknowledge signal, the transmitter removes the data from its output terminals. For example, the transmitter may drive each of its output signals to the same predetermined logic level to effectively tri-state the output terminals. In acknowledgement of this action by the transmitter, the receiver then asserts the acknowledge signal to begin another QDI cycle.
Operating frequencies of integrated circuits continue to increase from one generation of integrated circuits to the next, and certain circuits may be more sensitive to increased frequencies than others. For example, a conventional integrated circuit may include various synchronous-based frequency dividers and oscillators, circuits whose performances may be lacking as operating frequencies increase.
Thus, there is a continuing need for better ways for a technique and/or system to address one or more of the problems that are set forth above as well as address one or more problems that are not set forth above.